I want also report a bug.
******************** GHDL Bug occured ****************************
Please report this bug on http://gna.org/projects/ghdl
GHDL release: GHDL 0.31 (20140108) [Dunoon edition]
Compiled with GNAT Version: 4.8.3 20140627
In directory: /home/red/ghdl/
Command line:
/opt/ghdl/lib/gcc/x86_64-unknown-linux-gnu/4.8.2/ghdl1 --work=work
--workdir=work
-P/opt/ghdl/lib64/gcc/x86_64-unknown-linux-gnu/4.8.2/vhdl/lib//v93/std/
-P/opt/ghdl/lib64/gcc/x86_64-unknown-linux-gnu/4.8.2/vhdl/lib//v93/ieee/
-quiet -o work/tb_cosim.s tb_cosim.vhd
Exception TYPES.INTERNAL_ERROR raised
Exception information:
Exception name: TYPES.INTERNAL_ERROR
Message: sem_names.adb:1847
Call stack traceback locations:
0x61690f 0x617c72 0x61e5c7 0x61fb33 0x61e1b5 0x61fb33 0x61e1b5 0x61bdae
0x60a909 0x60b12e 0x62d868 0x624bf5 0x60bc95 0x62f6d5 0x60121b 0x6022e5
0x567ea5 0x54af93 0x555f44 0x557a28 0x54dac1 0x567ef9 0x549881
0x7f2ef3932b03 0x549a53 0xfffffffffffffffe
******************************************************************
Execution terminated by unhandled exception
Exception name: TYPES.INTERNAL_ERROR
Message: sem_names.adb:1847
Call stack traceback locations:
0x61690f 0x617c72 0x61e5c7 0x61fb33 0x61e1b5 0x61fb33 0x61e1b5 0x61bdae
0x60a909 0x60b12e 0x62d868 0x624bf5 0x60bc95 0x62f6d5 0x60121b 0x6022e5
0x567ea5 0x54af93 0x555f44 0x557a28 0x54dac1 0x567ef9 0x549881
0x7f2ef3932b03 0x549a53 0xfffffffffffffffe
ghdl: compilation error
makefile:7: recipe for target 'all' failed
make: *** [all] Error 1
red@linux-k4o7:~/ghdl>
all:
rm -rf work
mkdir work
ghdl -a --work=work --workdir=work sim_pkg.vhd
gcc -c -fPIC sim.c -o sim.o
ghdl -a --work=work --workdir=work tb_cosim.vhd
ghdl -e -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork
tb_cosim
# ghdl -r tb_lm_cpu
ghdl -r tb_cosim --wave=tbencha.ghw --stop-time=100ns
# ghdl -r tbench --disp-tree=inst --wave=tbench.ghw
# ghdl -r tb_lm_cpu
view:
gtkwave tbencha.ghw a.sav
post:
rm -rf work
mkdir work
ghdl -i ../ise601/netgen/synthesis/MAIS_soc_synthesis.vhd
ghdl -i ../rtl/tb_MAIS.vhd
ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/*.vhd
ghdl -i --work=unisim
/opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/primitive/*.vhd
ghdl -m -g -Punisim -Psimprim --warn-unused --ieee=synopsys
-fexplicit tb_lm_cpuvi
ghdl -r tb_lm_cpu --disp-tree=inst --wave=tbench.ghw --stop-time=50us
#include <stdio.h>
void street(int number)
{
printf("street: %d\n",number);
}
void house(int number)
{
printf("house: %d\n",number);
}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sim_pkg is
procedure house ( reg : in integer );
attribute foreign of house :
procedure is "VHPIDIRECT house";
procedure street ( reg : in integer );
attribute foreign of street :
procedure is "VHPIDIRECT street";
end;
package body sim_pkg is
procedure house (reg : in integer) is
begin
assert false report "VHPI" severity failure;
end house;
procedure street (reg : in integer) is
begin
assert false report "VHPI" severity failure;
end street;
end sim_pkg;
--------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sim_pkg.all;
entity tb_cosim is
end tb_cosim;
architecture behavior of tb_cosim is
function crc (crc_value : std_logic_vector(31 downto 0)
) return std_logic_vector is
variable crc_out : std_logic_vector(31 downto 0);
begin
crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc;
return crc_out;
end crc;
signal random : std_logic_vector ( 31 downto 0):=X"00000000";
-- Clock period definitions
constant board_clk_period : time := 20 ns;
signal board_clk: std_logic;
begin
process (board_clk)
begin
if rising_edge(board_clk) then
street(to_integer(unsigned(random)));
random<=crc(random);
end if;
end process;
-- Clock process definitions
board_clk_process : process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
end;
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