Hello,
I started to write a VHDL parser some weeks ago. It's written in Python with documentation extraction in mind. The parser supports VHDL-2008, I don't know if I want to support 2002, 93 or 87 too.
The parser is streaming oriented and needs several passes. Different proof of concepts show what's possible with my uncommon parsing approach. Sure it could be used for more complex flows like netlist generation, but I don't think if this is a good idea ...
Current /planned passes:
1. Character grouping as tokens (space, string, char)
2. Token replacement (e.g. by keyword tokens) and grouping into blocks
3.a) grouping blocks into groups (not published)
3.b) transform blocks into a VHDL DOM
4. resolve symbols (planned)
5. create an in-memory netlist
Possible use cases:
a) compile order extraction
b) documentation extraction (-> Shpinx / ReadTheDocs)
c) syntax highlightling / linked syntax
d) rewrite VHDL-2008 to synthesizable VHDL-93 code
c) rewrite to Verilog, ...
My code and an example is published at https://github.com/Paebbels/pyVHDLParser
The current code base is huge but very fast. There should be space for optimizations.
P.S. It's also possible to translate my parser into pure C with a simple stack, a record and one function pointer per state :).
Kind regards
Patrick
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
01062 Dresden, GERMANY
Tel.: +49 351 463-38451 Fax: +49 351 463-38324
E-Mail: patrick.lehm...@tu-dresden.de
WWW: http://vlsi-eda.inf.tu-dresden.de
-------- Ursprüngliche Nachricht --------
Von: Adrien Prost-Boucle
Datum:03.10.2016 20:09 (GMT+01:00)
An: GHDL discuss list
Betreff: Re: [Ghdl-discuss] Synthesis for FPGAs
Hi,
Synthesis and simulation are indeed completely different things.
There are a few Verilog-to-VHDL tools such as
vhdl2verilog http://www.edautils.com/vhdl2verilog.html
vhd2vl http://doolittle.icarus.com/~larry/vhd2vl/
vhdlpp https://github.com/steveicarus/iverilog/tree/master/vhdlpp
But all of them could implement their own, limited VHDL parser.
Limited as much in syntax checking and in functionalities and
conversion abilities.
As VHDL is a programming language with complicated features, I
think that parsing it is in fact a challenge.
Being able to reuse a good parser would be very helpful, and there
is no doubt GHDL's is the best out there in the open-source world.
Also, existing code introspection features certainly strongly help
conversion, for translation to Verilog as well as doing synthesis:
executing functions that just generate constants or do casts, etc.
Even if you consider that as the "simplest" part, it's still a big
part, and any reuse of good stuff would saves a lot of
reinvent-the-wheel time and allow to better focus on the the rest.
Regards,
Adrien
On Mon, 2016-10-03 at 19:18 +0200, Walter F.J. Mueller wrote:
> Hi all,
>
> open source synthesis is fine. Can be quite independent of the
> target device, with limited knowledge of it one can get probably
> quite far. Using such a tool to generate a netlist and the vendor
> tool chains for implementation ((place and route) and bitstream
> generation might be worth a try.
>
> But for the implementation step and bitstream generation, as tried
> in icestorm, one needs a very precise timing model and lots of other
> very deep knowledge about the target device. And in case of a mistake
> in implementation one can easily burn up an FPGA.
>
> And to your question: simulation, as done by ghdl, and synthesis, as
> done by Yosys, are very different things. They both start with a
> parser for the input language (VHDL), but that's in fact the simplest
> part.
>
>
> > With best regards, Walter
>
>
>
> On 10/03/2016 06:21 PM, Salvador Eduardo Tropea wrote:
> >
> > Hi All!
> >
> > > > Last year the first free software tool chain for FPGAs emerged. The IceStorm (http://www.clifford.at/icestorm/) project allows
> > synthesis from Verilog for Lattice iCE40 FPGAs.
> >
> > > > This tool-chain uses Yosys (http://www.clifford.at/yosys/) as base.
> >
> > > > But no VHDL. Recently Yodl (https://github.com/forflo/yodl) emerged. Yodl is an effort to do what Yosys does for Verilog, but for VHDL.
> >
> > I'm a complete ignorant about GHDL, Yosys and Yodl internals, but I'm curious about the synergy between GHDL and Yodl.
> >
> > I know GHDL is ADA code and I see Yodl is C++. But I see Yodl people having some problems (or doubts) about the VHDL parser.
> >
> > Just wondering ...
> >
> > Regards, Salvador
> >
> > P.D: I know IceStorm currently support http://www.edautils.com/vhdl2verilog.html and this is an incomplete solution.
> >
>
>
> _______________________________________________
> Ghdl-discuss mailing list
> Ghdl-discuss@gna.org
> https://mail.gna.org/listinfo/ghdl-discuss
_______________________________________________
Ghdl-discuss mailing list
Ghdl-discuss@gna.org
https://mail.gna.org/listinfo/ghdl-discuss
Synthesis and simulation are indeed completely different things.
There are a few Verilog-to-VHDL tools such as
vhdl2verilog http://www.edautils.com/vhdl2verilog.html
vhd2vl http://doolittle.icarus.com/~larry/vhd2vl/
vhdlpp https://github.com/steveicarus/iverilog/tree/master/vhdlpp
But all of them could implement their own, limited VHDL parser.
Limited as much in syntax checking and in functionalities and
conversion abilities.
As VHDL is a programming language with complicated features, I
think that parsing it is in fact a challenge.
Being able to reuse a good parser would be very helpful, and there
is no doubt GHDL's is the best out there in the open-source world.
Also, existing code introspection features certainly strongly help
conversion, for translation to Verilog as well as doing synthesis:
executing functions that just generate constants or do casts, etc.
Even if you consider that as the "simplest" part, it's still a big
part, and any reuse of good stuff would saves a lot of
reinvent-the-wheel time and allow to better focus on the the rest.
Regards,
Adrien
On Mon, 2016-10-03 at 19:18 +0200, Walter F.J. Mueller wrote:
> Hi all,
>
> open source synthesis is fine. Can be quite independent of the
> target device, with limited knowledge of it one can get probably
> quite far. Using such a tool to generate a netlist and the vendor
> tool chains for implementation ((place and route) and bitstream
> generation might be worth a try.
>
> But for the implementation step and bitstream generation, as tried
> in icestorm, one needs a very precise timing model and lots of other
> very deep knowledge about the target device. And in case of a mistake
> in implementation one can easily burn up an FPGA.
>
> And to your question: simulation, as done by ghdl, and synthesis, as
> done by Yosys, are very different things. They both start with a
> parser for the input language (VHDL), but that's in fact the simplest
> part.
>
>
> > With best regards, Walter
>
>
>
> On 10/03/2016 06:21 PM, Salvador Eduardo Tropea wrote:
> >
> > Hi All!
> >
> > > > Last year the first free software tool chain for FPGAs emerged. The IceStorm (http://www.clifford.at/icestorm/) project allows
> > synthesis from Verilog for Lattice iCE40 FPGAs.
> >
> > > > This tool-chain uses Yosys (http://www.clifford.at/yosys/) as base.
> >
> > > > But no VHDL. Recently Yodl (https://github.com/forflo/yodl) emerged. Yodl is an effort to do what Yosys does for Verilog, but for VHDL.
> >
> > I'm a complete ignorant about GHDL, Yosys and Yodl internals, but I'm curious about the synergy between GHDL and Yodl.
> >
> > I know GHDL is ADA code and I see Yodl is C++. But I see Yodl people having some problems (or doubts) about the VHDL parser.
> >
> > Just wondering ...
> >
> > Regards, Salvador
> >
> > P.D: I know IceStorm currently support http://www.edautils.com/vhdl2verilog.html and this is an incomplete solution.
> >
>
>
> _______________________________________________
> Ghdl-discuss mailing list
> Ghdl-discuss@gna.org
> https://mail.gna.org/listinfo/ghdl-discuss
_______________________________________________
Ghdl-discuss mailing list
Ghdl-discuss@gna.org
https://mail.gna.org/listinfo/ghdl-discuss
smime.p7s
Description: S/MIME Cryptographic Signature
_______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
