orpiske commented on a change in pull request #5: ARTEMIS-2533 Support multiple
architecture for ASYNCIO kernel by-pass
URL:
https://github.com/apache/activemq-artemis-native/pull/5#discussion_r340316928
##########
File path:
src/main/c/org_apache_activemq_artemis_nativo_jlibaio_LibaioContext.c
##########
@@ -32,15 +32,11 @@
#include <fcntl.h>
#include <stdlib.h>
#include <pthread.h>
+#include <stdatomic.h>
#include <limits.h>
#include "org_apache_activemq_artemis_nativo_jlibaio_LibaioContext.h"
#include "exception_helper.h"
-//x86 has a strong memory model and there is no need of HW fences if just
Write-Back (WB) memory is used
-#define mem_barrier() __asm__ __volatile__ ("":::"memory")
-#define read_barrier() __asm__ __volatile__("":::"memory")
-#define store_barrier() __asm__ __volatile__("":::"memory")
-
Review comment:
Exactly. atomic_thread_fence is provided by stdatomic which, in turn, is
only available on newer GCC. To work-around that, @franz1981 can probably do
some thing like this:
1. Add a check for stdatomic.h on the CMakeLists.txt and, based on its
presence, define a HAVE_STDATOMIC_H flag:
```
include (CheckIncludeFiles)
if (UNIX)
CHECK_INCLUDE_FILES(stdatomic.h HAVE_STDATOMIC_H)
endif (UNIX)
```
2. Define atomic_thread_fence as the previous memory barrier to retain the
current behaviour:
```
#if defined(HAVE_STDATOMIC_H)
#include <stdatomic.h>
#else
#define memory_order_acquire ""
#define memory_order_release ""
#define atomic_thread_fence(x) __asm__ __volatile__ ("":::"memory")
#endif
```
This should make the code build on older versions just like the current one.
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