@cousteaulecommandant commented on this pull request.
> @@ -788,6 +788,64 @@ static TMParserMapGroup group_VERILOG[] = {
{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
};
+static TMParserMapEntry map_SYSVERILOG[] = {
+ // Verilog and SystemVerilog
Makes sense once I replace that whole chunk with `COMMON_VERILOG`.
Should I also remove the ones in `group_[SYS]VERILOG`? I intend to merge the
two of them together and `#define group_SYSVERILOG group_VERILOG` so it might
get confusing.
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