@cousteaulecommandant pushed 4 commits. 5a31419ff0c4bbd3a6546cbf38295da2f1d87c72 Add SystemVerilog filetype 143cf1930b1b30a6ee2ad6fdd30ad02feb0b018b tagmanager: SystemVerilog: map ctags 6c1139c39eba96a0aad700cc0e85eb072fb4e36b tagmanager: Unify Verilog and SystemVerilog tags 26dc1eca5fbd522fa1d27a43605bb0a0092060ce Split SystemVerilog keywords into type / not type
-- View it on GitHub: https://github.com/geany/geany/pull/4039/files/10b4e937ac99acbdac03643ce4591159ef4759a6..26dc1eca5fbd522fa1d27a43605bb0a0092060ce You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/before/10b4e937ac99acbdac03643ce4591159ef4759a6/after/[email protected]>
