> There IS an oop package mapping,
Yeah, sorry, I was confused - I checked the `sysverilog.sv` test which had
"package" test unchecked in the top comment so I thought it wasn't mapped.
I think I know what is going on - it doesn't work for types that are declared
_after_ their members like
```verilog
typedef struct packed {
logic [7:0] data;
logic parity;
} struct_t;
```
where `struct_t` is behind `data` and `parity`. At least for C/C++ we dealt
with such situations already for typedefs and I think it would work if you used
`tm_tag_typedef_t` mapping but we should probably generalize it for other
mappings - I'd have to check the code.
In any case, nothing for this PR which I think is ready to be merged.
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