This seems to work with the example file I created (`tests/ctags/oop.sv`), and also with a small example I made. Thanks!
I found that this doesn't work if I declare the struct or typedef struct outside of a module, package, etc; but I'm not even sure that's legal in SystemVerilog. Probably not, so I wouldn't worry. -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4063#issuecomment-2492393562 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4063/[email protected]>
