zhanchangbao-sanechips commented on code in PR #51340:
URL: https://github.com/apache/arrow/pull/51340#discussion_r4407977469
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cpp/cmake_modules/SetupCxxFlags.cmake:
##########
@@ -547,6 +565,24 @@ if(ARROW_CPU_FLAG STREQUAL "aarch64")
message(WARNING "ARROW_SIMD_LEVEL=${ARROW_SIMD_LEVEL} not supported by
Arm.")
endif()
endif()
+if(ARROW_CPU_FLAG STREQUAL "riscv64")
+ if(ARROW_SIMD_LEVEL MATCHES "RVV")
+ if(NOT CXX_SUPPORTS_RVV)
+ message(FATAL_ERROR "RVV required but compiler doesn't support it.")
+ endif()
+ set(CXX_COMMON_FLAGS "${CXX_COMMON_FLAGS} -march=${ARROW_RVV_MARCH}")
+ string(REGEX MATCH "[0-9]+" RVV_VECTOR_BITS ${ARROW_SIMD_LEVEL})
+ if(RVV_VECTOR_BITS)
+ set(ARROW_HAVE_RVV${RVV_VECTOR_BITS} ON)
+ add_definitions(-DARROW_HAVE_RVV${RVV_VECTOR_BITS})
Review Comment:
GCC documentation (https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html)
shows -mrvv-vector-bits only accepts scalable/zvl (and pairs with a zvlXXXb
march extension), unlike SVE's direct -msve-vector-bits=N.
Fixing VLEN at compile time is also contrary to RVV's design: RVV is a
variable-length architecture and the vector length is selected at runtime via
vsetvl (xsimd's RVV backend is VLA as well). So the ARROW_HAVE_RVV${bits} macro
is a runtime dispatch tag rather than a compile-time vector width.
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