zhanchangbao-sanechips commented on code in PR #51340:
URL: https://github.com/apache/arrow/pull/51340#discussion_r4429970418
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cpp/cmake_modules/SetupCxxFlags.cmake:
##########
@@ -547,6 +565,24 @@ if(ARROW_CPU_FLAG STREQUAL "aarch64")
message(WARNING "ARROW_SIMD_LEVEL=${ARROW_SIMD_LEVEL} not supported by
Arm.")
endif()
endif()
+if(ARROW_CPU_FLAG STREQUAL "riscv64")
+ if(ARROW_SIMD_LEVEL MATCHES "RVV")
+ if(NOT CXX_SUPPORTS_RVV)
+ message(FATAL_ERROR "RVV required but compiler doesn't support it.")
+ endif()
+ set(CXX_COMMON_FLAGS "${CXX_COMMON_FLAGS} -march=${ARROW_RVV_MARCH}")
+ string(REGEX MATCH "[0-9]+" RVV_VECTOR_BITS ${ARROW_SIMD_LEVEL})
+ if(RVV_VECTOR_BITS)
+ set(ARROW_HAVE_RVV${RVV_VECTOR_BITS} ON)
+ add_definitions(-DARROW_HAVE_RVV${RVV_VECTOR_BITS})
Review Comment:
> Well, it looks like xsimd itself [uses something
like](https://github.com/xtensor-stack/xsimd/blob/ebe9991fb0e8ed2dfb7c1a9425aaf6b104adab86/cmake/Architecture.cmake#L121-L138)
`-march=rv64gcv_zvl${vector_bits} -mrvv-vector-bits=zvl`.
>
> I'm not sure how another approach would work. We need vectors to have a
well-known length at compile-time.
You're right — for a static fixed-width build we should fix the vector
length at compile time, matching xsimd. Updated the RVV${bits} branch to add
-march=${ARROW_RVV_MARCH}_zvl${bits}b -mrvv-vector-bits=zvl (guarded by
check_cxx_compiler_flag since GCC ≤ 13 doesn't support -mrvv-vector-bits),
while the sizeless RVV build keeps -march=rv64gcv.
Additionally, to align with SVE's ARROW_USER_SIMD_LEVEL support, I added a
RISC-V branch in cpu_info.cc so that
ARROW_USER_SIMD_LEVEL=RVV/RVV128/RVV256/RVV512 takes effect.
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