David Miller <[email protected]> writes: I'd suggest checking this code in at this point.
I decided to leave lshift, rshift, and lshiftc all separate for now. But I whacked the post loop code somewhat more. The lshiftc code runs at 3 c/l on US3, not the claimed 2.5 c/l. I suspect also the US1 claim if 2 c/l is invalid. It is not hard to see why it is 3 c/l. I haven't tried swapping things around to fix this, since that would risk hurting the T3/T4 performance. Perhaps you could look into that? My current versions of the files are attached.
sparc64-lshift.asm
Description: Binary data
sparc64-rshift.asm
Description: Binary data
sparc64-lshiftc.asm
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-- Torbjörn
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