Laurent Desnogues <laurent.desnog...@gmail.com> writes: > This is not completely correct: as soon as you have an out of order > micro architecture with register renaming, you'll have to add hardware > to also rename flags, so it's not 100% free.
There's a cost to having multiple outputs from the same instruction, so I can see some attraction in eliminating the carry flag (similar reasons that some architectures prefers a mulhi instructions over a "widening mul" instruction with two output registers). Additional inputs, e.g., two operands + carry in, is less of a problem than additional outputs. But if one designs the instruction set that way, so that two instructions are needed to get sum and carry out of two operands (or both halves of a full product), one ought to make sure that those two instructions can run in parallel. While on Risc V, it appears to take two *depending* instructions. (My toy architecture does have a single condition flag, which can be used as carry, see https://git.lysator.liu.se/nisse/instr16). Regards, /Niels -- Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677. Internet email is subject to wholesale government surveillance. _______________________________________________ gmp-devel mailing list gmp-devel@gmplib.org https://gmplib.org/mailman/listinfo/gmp-devel
