Hans Petter Selasky <h...@selasky.org> writes: > No, this is not what I tried to express. I meant that if the Risc-V is > modified to consumes a fixed number of parallell instructions, N, per > clock, instead of just one, that the performance would be comparable > to that of x86.
Not with the current instruction set. As Torbjörn has explained is some detail, you can produce difference and borrow with two *independent* instructions, so with sufficient parallelism (send the work to two independent execution units, running in parallel) you can get both in a single cycle. But to produce sum and carry out, you need two *dependent* instructions, so even if you have plenty of execution units to send the work to, it will still be two cycles. x86 (like most modern processors) will do it in one cycle. To get it into one cycle on RISC V, you would have to somehow fuse instructions, which is a lot more complexity than super-scalarity. And on top of that, there's also a severe penalty on carry *input*. Regards, /Niels -- Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677. Internet email is subject to wholesale government surveillance. _______________________________________________ gmp-devel mailing list gmp-devel@gmplib.org https://gmplib.org/mailman/listinfo/gmp-devel
