Hi, On Thu, Jul 26, 2012 at 8:39 PM, al davis <[email protected]> wrote:
> I built it as a plugin, > > g++ -I ./include -shared -fPIC -o gschem.so d_net.cc lang_gschem.cc > > where ./include is a symlink to where the gnucap include files are .. > > then tried it > I had to stub-out some functions to get it to load .. > I have been pushing intermediate work to the branch gschemnewstsh[1]. I'm sorry to have not mentioned it. I'll merge back to lang_gschem and clean up a bit and write a status report by tomorrow. I use "print" to check "parse" .. work on them as a pair, > so print is supposed to give back what went in. > 'list' on gschemnewstsh is printing the parsed items. > the verilog "module" is like a spice ".subckt" .. > The only use of a "module" here is that the schematic might > be contained in one. > Ok. So, module should be used for hierarchical schematics? [1] : github.com/savvy2020/gnucap/tree/gschemnewstsh/ -- Savant Krishna | Junior Undergraduate | Electrical Engineering | IIT Bombay _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
