On 07/26/2012 10:57 AM, [email protected] wrote:
Ok. So, module should be used for hierarchical schematics?
Yes, that's how hierarchy is specified in verilog. A module instance with its port names and numbers is the connection data to another schematic, or chunk of verilog code. If a verilog buss connects to multiple instances called out as the same module with instance numbers like [7:0] the same schematic or chunk of verilog code will be used 8 times in creating the circuit. But gschem has no way of executing that specification at present with names in verilog format. The names have to be unique and create a flat netlist is the way gschem does pseudo hierarchy now. It would be nice to have a netlist that used modules and instances and the subschematic was existing only once and when you changed it, all the instances would update. John Griessen _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
