Hi list.

i'm trying to extend the adms-mot/xml based code generator by
subdevices. this seems to be a very natural thing to do. also it looks
easy to implement, as gnucap already supports hierarchical netlists very
well...

also admsXml (2.3.0) has submodule capabilities. at least it parses and
processes things like
module foo(a,b)
..
endmodule
module bar(x,y)A
..
foo #(..) FOO (x,y)
endmodule
without much trouble.

but i have got no luck, either telling admsXml to take 'foo' from
somewhere else, or to keep shut about the undefined modulename. is it
correct that verilog/adms does not have a concept of forward
declarations or prototypes? thats what it seems to me after a web-search
and browsing the VAMS standard reference (2009, too old?) from
accellera. i am about to hack an "extern" keyword into the parser to
have something to work with, but i would like to have asked for
suggestions or alternatives first.

regards
felix

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