Hi
I haven't yet planned how to achieve the translation but VHDL, unlike Haskell, doesn't have type inference mechanisms. That means I need to declare the interface of whatever I will translate each Yhc.Core function to (i.e. VHDL Entities, Architectures, Functions ... )
Can you explain more about the "declare the interface" remark? I suspect this can be acheived with Yhc using the signatures from the .hi files, or embeding the information with our "typerep" Haskell extension.
It's true that the ExtCore rep is somewhat bit-rotted, but the only thing missing to get Core *output* is someone to beef up the pretty printer. I'd do it myself, except that there is a *design* task to do, namely to fix the concrete syntax for some of FC's constructs. One could choose anything, but it'd be good to choose a syntax that is easy to parse. Once the syntax is designed, it'd take an hour or two to make GHC emit it. (There's a separate job to make GHC parse and typecheck ExtCore as its source program, but you don't need that.)
For a reference point, I debated what the Yhc Core language should look like for a while. Then I gave up, grabbed a copy of DrIFT, adding "deriving Binary" annotations and was done. There is a concrete binary data type that represents Yhc.Core, but I have no idea what it is, and I certainly don't support access to it. There is a Haskell library which can load a Yhc.Core file, manipulate it, write it out etc - removing the need for a concrete syntax. We have a pretty printer, but since thats a one way mapping its much easier, we just made it look as much like Haskell as possible (no Z encoding etc). Thanks Neil _______________________________________________ Haskell-Cafe mailing list Haskell-Cafe@haskell.org http://www.haskell.org/mailman/listinfo/haskell-cafe
