On 3 Jun 2005 09:45:31 -0700,
[EMAIL PROTECTED] (Blaicher, Chris) wrote:
>For a fairly decent description, try looking at:
>
>http://lse.sourceforge.net/numa/faq/
That was a very helpful link; thanks for posting it! I've never dived this
deeply into hardware architecture; it's fascinating.
The z990 Reference Guide contains the statement:
All books are interconnected with a super-fast bi-directional
redundant ring structure which allows the system to be
operated and controlled by PR/SM operating in LPAR mode as a
symmetrical, memory coherent, multiprocessor.
After thinking about this passage, I have a couple of questions.
When a z990 contains more than one book, each book's local memory
obviously represents only a part of the system's total address space. Each
book needs some sort of address decode mechanism to determine whether a
particular address references memory local to the book or on another book
in the system. How is the base address of each book's memory assigned?
(Book A's local memory represents the first 16GiB, Book B the next 32GiB
and Book D the last 16GiB, for a total system memory of 64GiB, for
example.) Is this allocation done through some sort of configuration
process, or does the hardware handle the assignments?
When defining LPARs, it seems that there may be an advantage to having an
LPAR's address space backed by a single book's memory. For example,
defining an LPAR that used one processor from Book A, but 8GiB of memory
from Book A and 8GiB from Book B wouldn't seem as efficient as defining
the same LPAR using all 16GiB from Book A.
Forgive me if these questions seem a little basic, but I've never
configured zSeries hardware, especially on large systems that might
contain multiple books. Seems like system configuration on a large box
could get quite subtle!
Eric
--
Eric Chevalier E-mail: [EMAIL PROTECTED]
Web: www.tulsagrammer.com
Is that call really worth your child's life? HANG UP AND DRIVE!
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