-----Original Message----- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of McKown, John Sent: Tuesday, March 02, 2010 3:59 PM To: IBM-MAIN@bama.ua.edu Subject: z9 / z10 instruction speed(s)
There are multiple z9 "models". Each model has its own MSU rating, which is= basically related to the number of CPs enabled and their "speed". Now, I k= now that all the CPs on all z9 run same hardware speed. So, I'm wondering h= ow they are "knee capped"? Now, I know that the "knee capping" is done by l= oading in a specific MCL. So, I'm thinking that this somehow does something= like "inserts a wait state" during instruction processing. That is, the XY= Z instruction on all z9s run in the same amount of time. But there is "some= thing extra" done at the end of the XYZ instruction which causes a "wait" b= efore the next instruction is actually executed. Am I on the right track? O= r is it done is some other strange manner? <SNIP> >From somewhere in the hazy past, it had something to do with instruction fetch. So while instruction fetch was being held up for n microcode cycles, the pipe was being filled, effectively, with NOPR instructions. Regards, Steve Thompson -- Opinions expressed by this poster may not reflect those of poster's employer -- ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
