On Wed, Dec 1, 2010 at 10:25 AM, Tony Harminc <t...@harminc.net> wrote:

> On 1 December 2010 10:46, Edward Jaffe <edja...@phoenixsoftware.com>
> wrote:
>
> > You can use an ordinary branch instruction (e.g., BASSM 14,15) to branch
> to
> > code above the bar. If you're running enabled, you won't execute for
> long... :-D
>
> Just how does it fail? Is the PSW instruction address silently
> truncated upon return from an interrupt as a result of its having been
> saved in a legacy control block, leading to continued execution at a
> presumably incorrect address, or is there some active detection and
> abend? Something else? What if I install the same code at, say
> 00000000_00123000 and 00000070_00123000, and branch to the
> above-the-bar code?
>


The first level interrupt handlers are responsible for saving the status of
the interrupted work. If they detect execution above the bar they call RTM
and ruin your day.




> It is, though, curious that there must be, as Paul Gilmartin points
> out, quite a bit of infrastructure already there in support of 64-bit
> addresses. The real PSW is at all times beyond the early stage of IPL
> a zArch one of 128 bits, and it must be saved and restored properly,
> as must things like PER addresses in control registers. What remains
> to be done?
> <http://bama.ua.edu/archives/ibm-main.html>
>


there is a technique called "PSW scrunching" that allows saving an extended
PSW in a normal 8 byte PSW field when the instruction address is only 4
bytes. As you can probably imagine, there is literally no way to preserve
compatibility with the near infinite number of programs that currently
understand and inspect the task management control blocks, so while
execution above the bar is a goal, it is a long way off yet.



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