I would expect MVPG to be slow - given its history. If we no longer feel 
the need to go "the scenic route" :-) maybe it isn't.

Martin

Martin Packer,
Mainframe Performance Consultant, zChampion
Worldwide Banking Center of Excellence, IBM

+44-7802-245-584

email: martin_pac...@uk.ibm.com

Twitter / Facebook IDs: MartinPacker
Blog: 
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From:
Tony Harminc <t...@harminc.net>
To:
IBM-MAIN@bama.ua.edu
Date:
01/06/2011 18:40
Subject:
Re: What is the current feeling for MVC loop vs. MVCL?
Sent by:
IBM Mainframe Discussion List <IBM-MAIN@bama.ua.edu>



On 1 June 2011 12:32, Jim Mulder <d10j...@us.ibm.com> wrote:

>  If your 8K MVCLs have 4K-aligned sources and targets, then
> they may be taking advantage of the page mover hardware.  In that
> case, MVCs could be considerably slower.

I had been about to suggest the MVPG instruction, but it's quite
possible that MVCL will use the same infrastructure if circumstances
are right. One imagines that with fewer options and special cases to
evaluate, fewer registers to tie up and none to update, for MVPG the
setup would be shorter, and the execution at least as fast. But one's
imagination is often not a good guide; I have a rather casual
benchmark for these two (that is, MVCL of 4k on a page boundary vs
MVPG with no fancy options) that shows MVPG just barely beating MVCL
on a z10, and losing heavily on all earlier machines I had access to
(P390, zPDT, MP3000, FLEX/ES and z9).

John Gilmore's points are well taken. If I may suggest one more,
loosely put, it is to use instructions for what they are usually used
for (which is, even more approximately, what they are documented to be
used for). This is likely to take advantage of hardware optimizations
over time without forcing a tight binding to the hardware of the day.
The assembler programmer does not have an easy way to recompile and
take advantage of whatever the hardware implementors and compiler
designers have come up with since the code was written.

Tony H.

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