Level 2 cache is the reason I believe. Larger in the modules with 20 PUs.
Birger Heede
IBM Software Group
Richards.Bob wrote:
I believe this has been answered before. However, the reason is because of what happens in the manufacturing of the chips.
Some chips yield faster clocking results than the established minimum and maximum.
The best of the maximums are set aside and, voila, you have a turbo model. Those
below the minimum used to be sold to HDS! (only kidding about that last part...I
think) <grin>
Bob
-----Original Message-----
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED]
Sent: Friday, March 24, 2006 3:40 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: z900 "Capacity Models"?
I saw that too, from Cheryl's list. But if they don't, IBM's document
that I referred to is incorrect. It says that both the 10x and the 1Cx
models have a 1.3 nanosecond cycle time and the 2Cx and 21x models have
a 1.09 nanosecond cycle time. Maybe IBM did something different in
building the blocks or memory interleaving or something to get the
additional boost.
Ideas, anybody?
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