Binyamin: Are you trying to ensure that all CPUs will see the "new" values once you are done? Because that is what I assumed you were really after when I attempted to answered the question.
In order to do that, you must do an update that forces the other CPUs to "flush" or store the affected cache line(e) in their local cache before your update is started. In another life (Amdahl 5990 MDF development) we assisted this using a "pipe-cleaner" instruction (BR 0) Something like: BR 0 CSD x,y,zz BR 0 BR 0 This is a high-over head situation but is needed to force store of the current results of the current CPU and hold up fetch on this CPU for the CS/CSD to complete. Now, while this is going on, the other CPUs are signaled to store results that are part of the cache line(s) being affected by your CSD. [From the Programming Notes for Branch On Condition in the z/ARCH PoP: 4. Execution of BCR 15,0 (that is, an instruction with a value of 07F0 hex) may result in significant performance degradation. To ensure optimum performance, the program should avoid use of BCR 15,0 except in cases when the serialization or checkpoint-synchronization function is actually required.] And then you wonder what this MP overhead stuff is... Later, Steve Thompson ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
