=========================================
-----Original Message-----
From: "Thompson, Steve (SCI TW)" <[EMAIL PROTECTED]>
Sent: 7/27/2006 11:46 AM
To: "IBM-MAIN@BAMA.UA.EDU" <IBM-MAIN@BAMA.UA.EDU>
Subject: Re: Doing a LM of two words on a double word bounday - is it 
serialized?

Binyamin: 

Are you trying to ensure that all CPUs will see the "new" values once
you are done? Because that is what I assumed you were really after when
I attempted to answered the question.

In order to do that, you must do an update that forces the other CPUs to
"flush" or store the affected cache line(e) in their local cache before
your update is started.

In another life (Amdahl 5990 MDF development) we assisted this using a
"pipe-cleaner" instruction (BR 0) 

Something like:

  BR 0
  CSD x,y,zz
  BR 0
  BR 0 
/snip/
Steve Thompson
=========================================

I think CSD should be CDS. If you read the PoPs, you'll
see the CS/CDS/CSG/CDSG all perform check-point synchronization
before and after the operation. The "BR 0" is not needed.

There were instruction sequences in Amdahl 5990/5995 MDF
that used "NOPR 0" to fill the instruction pipeline to
compensate for some processing that may contaminate the
pipeline. I can't recall those weird situations at the moment.


Jeffrey D. Smith
Farsight Systems Corporation
24 BURLINGTON DR
LONGMONT, CO 80501
303-774-9381 direct
303-709-8153 cell
303-484-6170 fax

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