On Tue, 18 Dec 2012 06:11:29 -0600, Donald Likens wrote: >it would be nice to know the relative speed of every instruction. > >For example: > >C r15,zero >LTR r15,r15 > >I believe LTR is faster but how much?
It depends. The LTR probably completes in one clock cycle or less. How much less depends upon what other instructions are near it in the instruction stream. The latest processors can execute two or three instructions in the same clock cycle under ideal conditions. The Compare will require a memory reference to obtain the value of the data at "zero". If that storage location is in the L1 cache, it can be fetched with no delay. If not it will take longer. The following was taken from a SHARE session titled "What's new in z/OS" presented in Anaheim by John Eels. L1 cache - same cycle L2 cache - 4 cycles L3 cache in the same book - more than 100 cycles L3 cache in another book - more than 200 cycles real memory - about 850 cycles All of these assume that the virtual address translation information is available in the TLB. If not, three levels of region table, the segment table and the page table must all be accessed, with the same caveats for the time required for all five of these additional memory references. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
