Or you just could do an STFLE and check the facility bits... Joe
On Wed, Mar 15, 2023 at 10:52 AM P H < 000004843e86df79-dmarc-requ...@listserv.ua.edu> wrote: > This doc (url below) will give you a list of what is available/supported > on different generations of the current System z. However if you want to > know about a specific system you have then discuss with your IBM Rep who > will be able to give you a complete list of features (VPD) for your System. > > https://www.redbooks.ibm.com/abstracts/redp5157.html > > Regards > > Parwez Hamid > ________________________________ > From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf > of Ituriel do Neto <000003427ec2837d-dmarc-requ...@listserv.ua.edu> > Sent: 15 March 2023 13:30 > To: IBM-MAIN@LISTSERV.UA.EDU <IBM-MAIN@LISTSERV.UA.EDU> > Subject: Re: CS/CDS instruction > > Can we detect if a specific feature is available in the current hardware? > > > Best Regards > > Ituriel do Nascimento Neto > z/OS System Programmer > > > > > > > Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin < > 0000042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu: > > > > > > On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote: > > >If some particular instruction set feature is installed, the > >definition of ASI/AGSI is enhanced to serialize the update, making it > >a simpler solution than a CDS loop or PLO. > > > >In some performance testing a while back on a z14 or z15 which I think > >had the above serialization feature, the execution times for a very > >large number of executions of L / AHI / ST were very close to the same > >count of ASI. If I recall, the ASI was a few percent slower, I guess > >because of the serialization. I.e., unless you're doing abnormal > >tests as I did, you won't notice the difference. > > > > From the PoOps (excerpted): > The storage-operand update reference for the follow- ing > instructions appears to be an interlocked-update reference as > observed by other CPUs and channel programs. > > • TEST AND SET > • COMPARE AND SWAP > (of course) > > • AND (NI and NIY), when the interlocked-access facility 2 is installed > • OR (OI and OIY), when the interlocked-access facility 2 is installed > (at last!) > > • ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility > 1 is installed and the first operand is aligned on an integral > boundary corresponding to its size > > The feature-dependent instructions are treacherous. Programmers must > avoid them in multi-tasking code intended to be portable. > > I consider it bad hardware design to introduce feature-dependent > instructions. They should have remained invalid operations on models > lacking the interlock facility. > > I believe NI and OI are primeval: they antedate multiprocessors and > became unsafe only at the advent of multiprocessors. > > -- > gil > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
