shmuel+...@patriot.net (Shmuel Metz , Seymour J.) writes: > The wiki "chip" articles since at least Z196 have been about the > entire processor complex rather than about the chips themselves. I > wish that some of the IBM chip designers would be willing to take on > the task of editing those articles.
re: http://www.garlic.com/~lynn/2013k.html#6 IBM licenses POWER architecture to other vendors. however, claim is that at least half of the z196 per processor improvment over z10 was introduction of out-of-order execution, branch prediction, speculative executive ... features which have been part of RISC chips for decades. further use of out-of-order execution, branch prediction, speculative execution were used for z12 increase in per processor improvement over z196. issue is legacy implementation cache miss stalls the execution units and current cache miss memory access latency ... measured in number of processor cycles ... is on the order of 360 disk i/o (i.e. disk i/o latency measured in number of 360 processor cycles). out-of-order execution allows hardware analogy of multi-tasking / multi-threading/programming ... allowing to switch to some other work while current instruction is stalled waiting for memory access on cache miss. the other feature allowing hardware analogy of multi-tasking / muti-threading/programming is hyper-threading. I had gotten sucked into being asked to help when it was worked on for 370/195 (which never shipped). The issue for 370/195 was that pipeline peak throughput was 10mips ... but 370/195 didn't have branch prediction or speculative executive ... as a result conditional branches would stall the pipeline ... and most codes only achieved 5mips throughput. hyperthreading would provide emulated multiprocessing with two instruction streams ... which had a better chance of keeping the execution units operating at peak throughput. note that risc implementations have had throughput advantage of x86 for decades ... however the past several generations of x86 have actually gone to RISC cores with hardware layer that translates x86 instructions into risc micro-ops ... that largely mitigates the throughput differences between risc implementations and x86 implementations. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
