Robert Wessel <[email protected]> writes: > I'd be careful making that claim... > > A resource is: > > http://www.tech-news.com/publib/index.html > > Anyway, approximate price for a 485 MIPS 9021-9X2 in 2Q94 is $1.3M, > for a 78,426 MIPS 2827-7A1 in 3Q12 $33.1M. > > In terms of MIPS growth, that's 161-fold in 18 years, or about 33% per > year. > > In terms of cost-per-MIPS, that's 9.85-fold over that interval (taking > into account about 55% inflation over that interval), or about 14% per > year. > > Both are well below the slower (doubling every two years) version of > Moore's Law. OTOH, Moore was talking about the number of transistors > on a chip, not system performance or cost/performance, although those > are common interpretations.
industry standard for MIPS is dhrystones which is actually count of iterations compared to benchmark on 370/158 assumed to be 1mip processor. recent mainframes z900, 16 processors, 2.5BIPS (156MIPS/proc), Dec2000 z990, 32 processors, 9BIPS, (281MIPS/proc), 2003 z9, 54 processors, 18BIPS (333MIPS/proc), July2005 z10, 64 processors, 30BIPS (469MIPS/proc), Feb2008 z196, 80 processors, 50BIPS (625MIPS/proc), Jul2010 EC12, 101 processors, 75BIPS (743MIPS/proc), Aug2012 max configured z196 @50BIPS is $28M or $560k/BIPS max configured ec12 @75BIPS is $33M or $440k/BIPS and a processor is 743 times that of 370/158 from 40yrs ago. moore's law has been about circuit size decreasing ... early on benefited by getting more circuits on chip and performance having to go off-chip less (3033 started out as 168-3 logic mapped to 20% faster chips but had 10times circuits/chip, some last minute logic revision to better leverage going off-chip less got 3033 up to 50% faster than 168-3). note 2010 IBM had base list price for E5-2600 blade of $1815 that have been benchmarked at 527BIPS ... or $3.44/BIPS ... E5-2600 had two 8core chips ... for 16proc or 33BIPS/proc. there has been one turn of the process crank since then and they are just starting to benchmark the next turn of the process crank .... http://www.anandtech.com/show/8046/pricing-and-details-for-intels-devils-canyon-and-unlocked-pentium-leaked-online-i7-4790k-i5-4690k-g3258 note that manufactures are saying they now ship more server chips directly to large cloud operators (than to brand name server vendors like HP, DELL, IBM, etc) and the large cloud operators claim they assemble their own servers for 1/3rd the price of brand name vendors (say around $1/BIPS compared to around half-mil/BIPS for mainframe). one of the issues is that memory access latency hasn't kept up with increase in processor cycle performance ... when the memory access latency is counted in number of processor cycles ... it is about the same as 1960s disk access latency measured in number of 1960s 360 processor cycles. The increasing mismatch of memory access latency started to result in hardware processor design more akin to 360 software multitasking (overlapping execution while waiting for disk access) ... starting at least two decades ago in risc & i86 cisc processor designs ... out-of-order instruction execution, branch prediction, speculative execution, hyperthreading (continue executing other instructions while waiting for memory access). The claim is that similar features start to appear in z196, accounting for over half the increase in z196 per processor MIP rate (compared to z10 per processor MIP rate, at least half the 156MIPS increase from 469 to 625) because of starting to introduce similar features ... with some further introduction in ec12 (part of the 118MIPS increase from 625 to 743) -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
