On Fri, 29 Jul 2011 11:47:55 -0700 Keith Packard <kei...@keithp.com> wrote:
> On Fri, 29 Jul 2011 10:50:11 -0700, Jesse Barnes <jbar...@virtuousgeek.org> > wrote: > > > + flags |= FDI_PHASE_SYNC_OVR(pipe); > > + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ > > + flags |= FDI_PHASE_SYNC_EN(pipe); > > + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ > > + POSTING_READ(SOUTH_CHICKEN1); > > +} > > ooh, this even makes the sequence of two writes sound sensible. > > Reviewed-by: Keith Packard <kei...@keithp.com> > > You didn't happen to check the register values after doing this, did > you? Just to verify that all of the crazy math works, given that we > can't actually test whether this fixes anything. > Tricky. I need to call this in the gen6 and ivb training routines rather than the ilk one... Bits seem to be getting set correctly with the last patch. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
