On Tue, Jan 24, 2012 at 10:03:57PM +0000, paulo louro wrote: > > Very ugly hack, > In file ---> intel_display.c function --- > > ironlake_crtc_mode_set > temp = I915_READ(_TRANSACONF); I915_WRITE(_TRANSACONF, temp & > ~(7<<21)); > I915_WRITE( 0x60028, 0x00000000); //VSYNCSHIFT_A— Vertical Sync Shift > Register This register needs to be 0x00000000 for progressive mode > I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe)); > In file ---> i915_reg.h #define > PIPECONF_INTERLACE_W_FIELD_INDICATION (7 << 21) // ( 6 << 21) > Not sure why the PIPECONF MASK is 110 and not 111, from intel pdf 000b > Progressive Fetch / Progressive display / 001b PF-ID Progressive Fetch / > Interlaced display (HDMI) Requires panel fitting to be enabled
Wohoo, this is awesome. Can you maybe go right ahead and create a patch for this? Should be nothing more than checking for an interlaced mode and banging the right values into these registers ... Yours, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
