On Mon, 20 Feb 2017 15:08:40 +0100
Hans de Goede <hdego...@redhat.com> wrote:
> Execute MIPI_SEQ_DEASSERT_RESET before putting the device in ready
> state (LP-11), this is the sequence in which things should be done
> according to the spec.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index f4539f1..8408f59 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -666,10 +666,13 @@ static void intel_dsi_pre_enable(struct intel_encoder
> *encoder,
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
> msleep(intel_dsi->panel_on_delay);
>
> - /* put device in ready state */
> + /* Deassert reset */
I don't think the comment is really necessary.
> + intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> +
> + /* Put device in ready state (LP-11) */
> intel_dsi_device_ready(encoder);
>
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> + /* Send initialization commands in LP mode */
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
>
> /* Enable port in pre-enable phase itself because as per hw team
> @@ -762,6 +765,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
>
> + /* Transition to LP-00 */
> intel_dsi_clear_device_ready(encoder);
>
> if (IS_BROXTON(dev_priv)) {
> @@ -785,6 +789,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
> I915_WRITE(DSPCLK_GATE_D, val);
> }
>
> + /* Assert reset */
Again, the comment doesn't provide any additional info.
But the rest looks good.
Reviewed-by: Bob Paauwe <bob.j.paa...@intel.com>
> intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
>
> /* Power off, try both CRC pmic gpio and VBT */
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
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