When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by: Matthew Auld <matthew.a...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b5b7372fcddc..4bb5b518aa00 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8307,10 +8307,13 @@ static void broadwell_init_clock_gating(struct
drm_i915_private *dev_priv)
/*
* WaGttCachingOffByDefault:bdw
- * GTT cache may not work with big pages, so if those
- * are ever enabled GTT cache may need to be disabled.
+ * The GTT cache must be disabled if the system is planning to use
+ * 2M/1G pages.
*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ I915_WRITE(HSW_GTT_CACHE_EN,
+ HAS_PAGE_SIZE(dev_priv,
+ I915_GTT_PAGE_SIZE_2M |
+ I915_GTT_PAGE_SIZE_1G) ? 0 : GTT_CACHE_EN_ALL);
/* WaKVMNotificationOnConfigChange:bdw */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
--
2.9.4
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