[Intel-gfx] [PATCH v2 5/9] drm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submission

[Zhi Wang]

Move tlb_handle_pending into intel_vgpu_submssion since it belongs to a
part of vGPU submission stuffs

Signed-off-by: Zhi Wang <zhi.a.w...@intel.com>
---
 drivers/gpu/drm/i915/gvt/gvt.h       | 2 +-
 drivers/gpu/drm/i915/gvt/handlers.c  | 2 +-
 drivers/gpu/drm/i915/gvt/render.c    | 3 ++-
 drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
 drivers/gpu/drm/i915/gvt/vgpu.c      | 1 -
 5 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index c3f84f2..93ff530 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -149,6 +149,7 @@ struct intel_vgpu_submission {
        atomic_t running_workload_num;
        struct i915_gem_context *shadow_ctx;
        DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
+       DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
 };
 
 struct intel_vgpu {
@@ -174,7 +175,6 @@ struct intel_vgpu {
        /* 1/2K for each reserve ring buffer */
        void *reserve_ring_buffer_va[I915_NUM_ENGINES];
        int reserve_ring_buffer_size[I915_NUM_ENGINES];
-       DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
 
 
 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index a1963fc..2ee494b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1537,7 +1537,7 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu 
*vgpu,
        default:
                return -EINVAL;
        }
-       set_bit(id, (void *)vgpu->tlb_handle_pending);
+       set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
 
        return 0;
 }
diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 7ed76ae..3910832 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -147,6 +147,7 @@ static u32 gen9_render_mocs_L3[32];
 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
 {
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+       struct intel_vgpu_submission *s = &vgpu->submission;
        enum forcewake_domains fw;
        i915_reg_t reg;
        u32 regs[] = {
@@ -160,7 +161,7 @@ static void handle_tlb_pending_event(struct intel_vgpu 
*vgpu, int ring_id)
        if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
                return;
 
-       if (!test_and_clear_bit(ring_id, (void *)vgpu->tlb_handle_pending))
+       if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
                return;
 
        reg = _MMIO(regs[ring_id]);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 3527daf..c880866 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -767,6 +767,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
                INIT_LIST_HEAD(&s->workload_q_head[i]);
 
        atomic_set(&s->running_workload_num, 0);
+       bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
 
        return 0;
 
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 35a5ec2..1c9818d 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -346,7 +346,6 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct 
intel_gvt *gvt,
        vgpu->handle = param->handle;
        vgpu->gvt = gvt;
        vgpu->sched_ctl.weight = param->weight;
-       bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
 
        intel_vgpu_init_cfg_space(vgpu, param->primary);
 
-- 
2.7.4

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