Quoting Matthew Auld (2017-09-22 18:32:48) > +static int igt_write_huge(struct drm_i915_gem_object *obj) > +{ > + struct drm_i915_private *i915 = to_i915(obj->base.dev); > + struct i915_gem_context *ctx = i915->kernel_context; > + struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->base : > &i915->ggtt.base; > + struct i915_vma *vma; > + unsigned int flags = PIN_USER | PIN_OFFSET_FIXED; > + unsigned int max_page_size; > + IGT_TIMEOUT(end_time); > + u32 max; > + u32 num; > + u64 size; > + int err; > + > + GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); > + > + size = obj->base.size; > + if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) > + size = round_up(size, I915_GTT_PAGE_SIZE_2M); > + > + max_page_size = rounddown_pow_of_two(obj->mm.page_sizes.sg); > + max = (vm->total - size) / max_page_size; > + > + vma = i915_vma_instance(obj, vm, NULL); > + if (IS_ERR(vma)) > + return PTR_ERR(vma); > + > + /* Try various offsets until we timeout -- we want to avoid > + * issues hidden by effectively always using offset = 0. > + */ > + for_each_prime_number_from(num, 0, max) { > + u64 offset = num * max_page_size; > + u32 dword; > + > + err = i915_vma_unbind(vma); > + if (err) > + goto out_vma_close; > + > + err = i915_vma_pin(vma, size, max_page_size, flags | offset); > + if (err) { > + /* The ggtt may have some pages reserved so > + * refrain from erroring out. > + */ > + if (err == -ENOSPC && i915_is_ggtt(vm)) > + continue; > + > + goto out_vma_close; > + } > + > + err = igt_check_page_sizes(vma); > + if (err) > + goto out_vma_unpin; > + > + dword = offset_in_page(num) / 4; > + > + err = gpu_write(vma, ctx, dword, num + 1);
We are restricting ourselves to only testing RCS. That feels like an oversight; RCS tends to have special page table handling which may mean we miss a bug on xCS. I would run each engine for timeout. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx