Matthew Auld <matthew.a...@intel.com> writes:
> Before we can enable 64K pages through the IPS bit, we must first enable
> it through MMIO, otherwise the page-walker will simply ignore it.
>
> v2: add comment mentioning that 64K is BDW+
>
> Signed-off-by: Matthew Auld <matthew.a...@intel.com>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ae7b683437f1..2fab70ad169e 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4755,6 +4755,22 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> }
> }
>
> + /* To support 64K PTEs we need to first enable the use of the
> + * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
> + * mmio, otherwise the page-walker will simply ignore the IPS bit. This
> + * shouldn't be needed after GEN10.
> + *
> + * 64K pages were first introduced from BDW+, although technically they
> + * only *work* from gen9+. For pre-BDW we instead have the option for
> + * 32K pages, but we don't currently have any support for it in our
> + * driver.
> + */
> + if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
> + INTEL_GEN(dev_priv) <= 10)
> + I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
> + I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
> + GAMW_ECO_ENABLE_64K_IPS_FIELD);
> +
Apparently we need this prior touching pde. Move this to
gtt_write_workarounds() and you can add my,
Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> i915_gem_init_swizzling(dev_priv);
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd0cd94..6fdcaec0e2ee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2371,6 +2371,9 @@ enum i915_power_well_id {
> #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
> #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
>
> +#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
> +#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
> +
> #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
> #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
> #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
> --
> 2.13.5
>
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