To their rightful place inside intel_workarounds.c v2: Classify WaDisableCSUnitClockGating and WaDisableSDEUnitClockGating as GT WAs
v3: - Static tables (Joonas) - Also move WaProgramL3SqcReg1Default/WaTempDisableDOPClkGating Signed-off-by: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> (v1) Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 39 +------------------- drivers/gpu/drm/i915/intel_workarounds.c | 63 +++++++++++++++++++++++++++++--- 2 files changed, 59 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index eb5bac0..aef0aee 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8705,40 +8705,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } -static void chv_init_clock_gating(struct drm_i915_private *dev_priv) -{ - /* WaVSRefCountFullforceMissDisable:chv */ - /* WaDSRefCountFullforceMissDisable:chv */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & - ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); - - /* WaDisableSemaphoreAndSyncFlipWait:chv */ - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); - - /* WaDisableCSUnitClockGating:chv */ - I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | - GEN6_CSUNIT_CLOCK_GATE_DISABLE); - - /* WaDisableSDEUnitClockGating:chv */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); - - /* - * WaProgramL3SqcReg1Default:chv - * See gfxspecs/Related Documents/Performance Guide/ - * LSQC Setting Recommendations. - */ - gen8_set_l3sqc_credits(dev_priv, 38, 2); - - /* - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. - */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); -} - static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) { uint32_t dspclk_gate; @@ -8867,12 +8833,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv)) + IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv) || + IS_CHERRYVIEW(dev_priv)) dev_priv->display.init_clock_gating = nop_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = bdw_init_clock_gating; - else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.init_clock_gating = chv_init_clock_gating; else if (IS_HASWELL(dev_priv)) dev_priv->display.init_clock_gating = hsw_init_clock_gating; else if (IS_IVYBRIDGE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 0e3f7c3..1ebce4f 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -646,10 +646,67 @@ static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv, static struct i915_wa_reg gen8_gt_was[] = { }; +/* WaTempDisableDOPClkGating */ +static bool disable_dop_clock_gating(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa) +{ + u32 misccpctl = I915_READ(GEN7_MISCCPCTL); + + wa->hook_data = misccpctl; + I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); + + return true; +} + +/* WaTempDisableDOPClkGating */ +static void enable_dop_clock_gating(struct drm_i915_private *dev_priv, + struct i915_wa_reg *wa) +{ + u32 misccpctl = wa->hook_data; + + /* + * Wait at least 100 clocks before re-enabling clock + * gating. See the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); + I915_WRITE(GEN7_MISCCPCTL, misccpctl); +} + static struct i915_wa_reg bdw_gt_was[] = { }; static struct i915_wa_reg chv_gt_was[] = { + { WA_GT("WaVSRefCountFullforceMissDisable + WaDSRefCountFullforceMissDisable"), + ALL_REVS, REG(GEN7_FF_THREAD_MODE), + CLEAR_BIT(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME) }, + + { WA_GT("WaDisableSemaphoreAndSyncFlipWait"), + ALL_REVS, REG(GEN6_RC_SLEEP_PSMI_CONTROL), + SET_BIT_MASKED(GEN8_RC_SEMA_IDLE_MSG_DISABLE) }, + + { WA_GT("WaDisableCSUnitClockGating"), + ALL_REVS, REG(GEN6_UCGCTL1), + SET_BIT(GEN6_CSUNIT_CLOCK_GATE_DISABLE) }, + + { WA_GT("WaDisableSDEUnitClockGating"), + ALL_REVS, REG(GEN8_UCGCTL6), + SET_BIT(GEN8_SDEUNIT_CLOCK_GATE_DISABLE) }, + + { WA_GT("WaProgramL3SqcReg1Default"), + ALL_REVS, REG(GEN8_L3SQCREG1), + SET_FIELD(L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(38) | L3_HIGH_PRIO_CREDITS(2)), + .pre_hook = disable_dop_clock_gating, + .post_hook = enable_dop_clock_gating }, + + /* + * GTT cache may not work with big pages, so if those + * are ever enabled GTT cache may need to be disabled. + */ + { WA_GT(""), + ALL_REVS, REG(HSW_GTT_CACHE_EN), + SET_FIELD(0xFFFFFFFF, GTT_CACHE_EN_ALL) }, }; static struct i915_wa_reg gen9_gt_was[] = { @@ -808,7 +865,6 @@ static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv, }; static const struct i915_wa_reg_table chv_gt_wa_tbl[] = { - { gen8_gt_was, ARRAY_SIZE(gen8_gt_was) }, { chv_gt_was, ARRAY_SIZE(chv_gt_was) }, }; @@ -897,9 +953,6 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) static struct i915_wa_reg bdw_disp_was[] = { }; -static struct i915_wa_reg chv_disp_was[] = { -}; - static struct i915_wa_reg gen9_disp_was[] = { /* * Must match Sampler, Pixel Back End, and Media. See @@ -1028,8 +1081,6 @@ static bool has_pch_cnp(struct drm_i915_private *dev_priv, }; static const struct i915_wa_reg_table chv_disp_wa_tbl[] = { - { gen8_disp_was, ARRAY_SIZE(gen8_disp_was) }, - { chv_disp_was, ARRAY_SIZE(chv_disp_was) }, }; static const struct i915_wa_reg_table skl_disp_wa_tbl[] = { -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx