On Mon, 15 Oct 2012, Paulo Zanoni <przan...@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> Just a missing register. There is no problem to run this code when the
> output is HDMI.

Reviewed-by: Jani Nikula <jani.nik...@intel.com>

>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 5071370..4f03b1b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1105,14 +1105,23 @@ void intel_ddi_post_disable(struct intel_encoder 
> *intel_encoder)
>       struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>       enum port port = intel_ddi_get_encoder_port(intel_encoder);
>       uint32_t val;
> +     bool wait = false;
>  
>       val = I915_READ(DDI_BUF_CTL(port));
>       if (val & DDI_BUF_CTL_ENABLE) {
>               val &= ~DDI_BUF_CTL_ENABLE;
>               I915_WRITE(DDI_BUF_CTL(port), val);
> -             intel_wait_ddi_buf_idle(dev_priv, port);
> +             wait = true;
>       }
>  
> +     val = I915_READ(DP_TP_CTL(port));
> +     val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> +     val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +     I915_WRITE(DP_TP_CTL(port), val);
> +
> +     if (wait)
> +             intel_wait_ddi_buf_idle(dev_priv, port);
> +
>       I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
>  }
>  
> -- 
> 1.7.11.4
>
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