On Mon, 15 Oct 2012, Paulo Zanoni <przan...@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> Much simpler and looks more like the M/N code inside intel_display.c.
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b10f35b..52b5453 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -794,9 +794,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
> drm_display_mode *mode,
> mode->clock, adjusted_mode->clock, &m_n);
>
> if (HAS_PCH_SPLIT(dev)) {
> - I915_WRITE(TRANSDATA_M1(pipe),
> - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
> - m_n.gmch_m);
> + I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
> I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
> I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
> @@ -807,8 +805,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct
> drm_display_mode *mode,
> I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> } else {
> I915_WRITE(PIPE_GMCH_DATA_M(pipe),
> - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
> - m_n.gmch_m);
> + TU_SIZE(m_n.tu) | m_n.gmch_m);
> I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
> I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
> I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
> --
> 1.7.11.4
>
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