Oscar Mateo <oscar.ma...@intel.com> writes:
> Avoids a hang during soft reset.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1405476379
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8caf42f..8da119f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9895,6 +9895,11 @@ enum skl_power_gate {
> #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers
> */
> #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS
> registers */
>
> +#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
> +#define PMFLUSHDONE_LNICRSDROP (1 << 20)
> +#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
> +#define PMFLUSHDONE_LNEBLK (1 << 22)
> +
> /* gamt regs */
> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for
> LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 35f2de3..f89a5c2 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -761,6 +761,14 @@ static void icl_gt_workarounds_apply(struct
> drm_i915_private *dev_priv)
> I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
> (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
> CGPSF_CLKGATE_DIS));
> +
> + /* WaForwardProgressSoftReset:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> + I915_WRITE(GEN10_SCRATCH_LNCF2,
> + (I915_READ(GEN10_SCRATCH_LNCF2) |
> + PMFLUSHDONE_LNICRSDROP |
> + PMFLUSH_GAPL3UNBLOCK |
> + PMFLUSHDONE_LNEBLK));
The references on this are someone contradicting.
I did found anything that would point it being fixed in C0
even tho wa database says that for B0.
Bspec says that you must set these unconditionally.
I would go with the bspec and unconditionally enable these
three bits.
-Mika
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 1.9.1
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