From: Manasi Navare <manasi.d.nav...@intel.com>
DFLEXDPMLE register is required to tell the FIA hardware which
main links of DP are enabled on TCC Connectors. FIA uses this
information to program PHY to Controller signal mapping.
This register is applicable in both TC connector's Alternate mode
as well as DP connector mode.
Cc: Jani Nikula <jani.nik...@linux.intel.com>
Cc: Animesh Manna <animesh.ma...@intel.com>
Cc: Madhav Chauhan <madhav.chau...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28ce96ce0484..7f27fe2e38c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,6 +1990,11 @@ enum i915_power_well_id {
_ICL_PORT_COMP_DW10_A, \
_ICL_PORT_COMP_DW10_B)
+/* ICL PHY DFLEX registers */
+#define ICL_PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
+#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
+
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
--
2.14.3
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