Em Ter, 2018-05-22 às 14:44 +0300, Mika Kahola escreveu:
> On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.nav...@intel.com>
> >
> > PLLs are the source clocks for the DDIs so in order
> > to determine the ddi clock we need to check the PLL
> > configuration.
> >
> > This gets a little tricky for ICL since there is
> > no register bit that maps directly to the link clock.
> > So this patch creates a separate function in intel_dpll_mgr.c
> > to obtain the write array PLL Params and compares the set
> > pll_params with the table to get the corresponding link
> > clock.
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Mika Kahola <mika.kah...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++
> > drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 66
> > +++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
> > 4 files changed, 97 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7f27fe2e38c7..26903cffabf6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9182,13 +9182,16 @@ enum skl_power_gate {
> > #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> > #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> > #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> > +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> > #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> > #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> > +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> > #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> > #define DPLL_CFGCR1_KDIV_1 (1 << 6)
> > #define DPLL_CFGCR1_KDIV_2 (2 << 6)
> > #define DPLL_CFGCR1_KDIV_4 (4 << 6)
> > #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> > +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> > #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> > #define DPLL_CFGCR1_PDIV_2 (1 << 2)
> > #define DPLL_CFGCR1_PDIV_3 (2 << 2)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index d8ae82001f83..0d8bed8e2200 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1458,6 +1458,30 @@ static void ddi_dotclock_get(struct
> > intel_crtc_state *pipe_config)
> > pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> > }
> >
> > +static void icl_ddi_clock_get(struct intel_encoder *encoder,
> > + struct intel_crtc_state
> > *pipe_config)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > > base.dev);
> >
> > + enum port port = encoder->port;
> > + int link_clock = 0;
> > + uint32_t pll_id;
> > +
> > + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config-
> > > shared_dpll);
> >
> > + if (port == PORT_A || port == PORT_B) {
> > + if (encoder->type == INTEL_OUTPUT_HDMI)
> > + link_clock = cnl_calc_wrpll_link(dev_priv,
> > pll_id);
> > + else
> > + link_clock =
> > icl_calc_dp_combo_pll_link(dev_priv,
> > + pl
> > l_
> > id);
> > + } else {
> > + /* FIXME - Add for MG PLL */
> > + WARN(1, "MG PLL clock_get code not implemented
> > yet\n");
> > + }
> > +
> > + pipe_config->port_clock = link_clock;
> > + ddi_dotclock_get(pipe_config);
> > +}
> > +
> > static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> > struct intel_crtc_state
> > *pipe_config)
> > {
> > @@ -1651,6 +1675,8 @@ static void intel_ddi_clock_get(struct
> > intel_encoder *encoder,
> > bxt_ddi_clock_get(encoder, pipe_config);
> > else if (IS_CANNONLAKE(dev_priv))
> > cnl_ddi_clock_get(encoder, pipe_config);
> > + else if (IS_ICELAKE(dev_priv))
> > + icl_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > void intel_ddi_set_pipe_settings(const struct intel_crtc_state
> > *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 383fbc15113d..3cc837f74ffb 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2525,6 +2525,72 @@ static bool icl_calc_dpll_state(struct
> > intel_crtc_state *crtc_state,
> > return true;
> > }
> >
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id)
> > +{
> > + uint32_t cfgcr0, cfgcr1;
> > + uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer,
> > dco_fraction;
> > + const struct skl_wrpll_params *params;
> > + int index, n_entries, link_clock = 0;
> > +
> > + /* Read back values from DPLL CFGCR registers */
> > + cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> > + cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> > +
> > + dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> > + dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > + DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> > + pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >>
> > DPLL_CFGCR1_PDIV_SHIFT;
> > + kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >>
> > DPLL_CFGCR1_KDIV_SHIFT;
> > + qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
> > + DPLL_CFGCR1_QDIV_MODE_SHIFT;
> > + qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> > + DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> > +
> > + params = dev_priv->cdclk.hw.ref == 24000 ?
> > + icl_dp_combo_pll_24MHz_values :
> > + icl_dp_combo_pll_19_2MHz_values;
> > + n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
> > +
> > + for (index = 0; index < n_entries; index++) {
> > + if (dco_integer == params[index].dco_integer &&
> > + dco_fraction == params[index].dco_fraction &&
> > + pdiv == params[index].pdiv &&
> > + kdiv == params[index].kdiv &&
> > + qdiv_mode == params[index].qdiv_mode &&
> > + qdiv_ratio == params[index].qdiv_ratio)
> > + break;
> > + }
> > + WARN(index == n_entries, "Invalid PLL Parameters");
> > +
> > + /* Map PLL Index to Link Clock */
> > + switch (index) {
> > + case 0:
> > + link_clock = 540000;
> > + break;
> > + case 1:
> > + link_clock = 270000;
> > + break;
> > + case 2:
> > + link_clock = 162000;
> > + break;
> > + case 3:
> > + link_clock = 324000;
> > + break;
> > + case 4:
> > + link_clock = 432000;
> > + break;
> > + case 5:
> > + link_clock = 432000;
> > + break;
> > + case 6:
> > + link_clock = 810000;
> > + break;
>
> Just to play it safe, we could add
>
> default:
> MISSING_CASE();
> }
>
> here and return with some default link clock value.
In this case the WARN above should be triggered and we'll return 0 (due
to link_clock being initialized to 0 at definition), but I would
prefer if our code was a little more explicit like you're suggesting,
especially removing the zero initialization, which only serves to hide
details like that.
Also, the table is wrong: it has 432 twice and is missing 216 and 648.
>
> > +
> > + return link_clock;
> > +}
> > +
> > static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> > {
> > return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index 7a0cd564a9ee..78915057d2e6 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -336,5 +336,7 @@ void intel_shared_dpll_init(struct drm_device
> > *dev);
> >
> > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> > struct intel_dpll_hw_state
> > *hw_state);
> > +int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> > + uint32_t pll_id);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
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