Em Qui, 2018-06-14 às 12:54 -0700, Dhinakaran Pandiyan escreveu:
> The Graphics System Event(GSE) interrupt bit has a new location in
> the
> GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the
> only
> DE_MISC interrupt that was enabled, with this change we don't
> enable/handle
> any of DE_MISC interrupts for gen11. Credits to Paulo for pointing
> out
> the register change.
>
> v2: from DK
> raw_reg_[read/write], branch prediction hint and drop platform check
> (Mika)
>
> v3: From DK
> Early re-enable of master interrupt (Chris)
Looks like all the requests have been implemented:
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> [Paulo: bikesheds and rebases]
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 46
> ++++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 2 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index c52060a35317..c7bd6caa98ea 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2946,11 +2946,44 @@ gen11_gt_irq_handler(struct drm_i915_private
> * const i915,
> spin_unlock(&i915->irq_lock);
> }
>
> +static void
> +gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32
> master_ctl,
> + u32 *iir)
> +{
> + void __iomem * const regs = dev_priv->regs;
> +
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return;
> +
> + *iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> + if (likely(*iir))
> + raw_reg_write(regs, GEN11_GU_MISC_IIR, *iir);
> +}
> +
> +static void
> +gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv,
> + const u32 master_ctl, const u32 iir)
> +{
> + if (!(master_ctl & GEN11_GU_MISC_IRQ))
> + return;
> +
> + if (unlikely(!iir)) {
> + DRM_ERROR("GU_MISC iir blank!\n");
> + return;
> + }
> +
> + if (iir & GEN11_GU_MISC_GSE)
> + intel_opregion_asle_intr(dev_priv);
> + else
> + DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n",
> iir);
> +}
> +
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = to_i915(arg);
> void __iomem * const regs = i915->regs;
> u32 master_ctl;
> + u32 gu_misc_iir;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
> @@ -2979,9 +3012,13 @@ static irqreturn_t gen11_irq_handler(int irq,
> void *arg)
> enable_rpm_wakeref_asserts(i915);
> }
>
> + gen11_gu_misc_irq_ack(i915, master_ctl, &gu_misc_iir);
> +
> /* Acknowledge and enable interrupts. */
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
> master_ctl);
>
> + gen11_gu_misc_irq_handler(i915, master_ctl, gu_misc_iir);
> +
> return IRQ_HANDLED;
> }
>
> @@ -3468,6 +3505,7 @@ static void gen11_irq_reset(struct drm_device
> *dev)
>
> GEN3_IRQ_RESET(GEN8_DE_PORT_);
> GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN11_GU_MISC_);
> GEN3_IRQ_RESET(GEN8_PCU_);
> }
>
> @@ -3911,9 +3949,12 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> uint32_t de_pipe_enables;
> u32 de_port_masked = GEN8_AUX_CHANNEL_A;
> u32 de_port_enables;
> - u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR;
> + u32 de_misc_masked = GEN8_DE_EDP_PSR;
> enum pipe pipe;
>
> + if (INTEL_GEN(dev_priv) <= 10)
> + de_misc_masked |= GEN8_DE_MISC_GSE;
> +
> if (INTEL_GEN(dev_priv) >= 9) {
> de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B |
> GEN9_AUX_CHANNEL_C |
> @@ -4010,10 +4051,13 @@ static void gen11_gt_irq_postinstall(struct
> drm_i915_private *dev_priv)
> static int gen11_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>
> gen11_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> + GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked,
> gu_misc_masked);
> +
> I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>
> I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 140f6a27d696..e4aebccf4461 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7053,9 +7053,16 @@ enum {
> #define GEN8_PCU_IIR _MMIO(0x444e8)
> #define GEN8_PCU_IER _MMIO(0x444ec)
>
> +#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER _MMIO(0x444fc)
> +#define GEN11_GU_MISC_GSE (1 << 27)
> +
> #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
> #define GEN11_MASTER_IRQ (1 << 31)
> #define GEN11_PCU_IRQ (1 << 30)
> +#define GEN11_GU_MISC_IRQ (1 << 29)
> #define GEN11_DISPLAY_IRQ (1 << 16)
> #define GEN11_GT_DW_IRQ(x) (1 << (x))
> #define GEN11_GT_DW1_IRQ (1 << 1)
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