On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote:
> This interlaced restriction applies to all gens, not only to Haswell.
I believe this came from VLV times and I doubt we would be
impacted by it ever, but better to protect just in case:
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index a84da931c3be..bb97c1657493 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> - if (IS_HASWELL(dev_priv) &&
> - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> return;
> }
> --
> 2.21.0
>
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