From: Michel Thierry <michel.thie...@intel.com>
Inherit workarounds from previous platforms that are still valid for
Tigerlake.
WaPipelineFlushCoherentLines:tgl (changed register but has same name)
WaSendPushConstantsFromMMIO:tgl
WaAllowUMDToModifySamplerMode:tgl
WaRsForcewakeAddDelayForAck:tgl
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Michel Thierry <michel.thie...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
5 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9e0992498087..239d2bc41e32 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2045,6 +2045,8 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
return 0;
switch (INTEL_GEN(engine->i915)) {
+ case 12:
+ return 0;
case 11:
return 0;
case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b1fc7c8faa8..ed92738a0735 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -582,6 +582,11 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
}
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -594,7 +599,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -895,10 +902,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1188,6 +1202,17 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
}
}
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ /* WaSendPushConstantsFromMMIO:tgl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifySamplerMode:tgl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1195,7 +1220,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_whitelist_build(engine);
+ else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
@@ -1245,6 +1272,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_GEN(i915, 12)) {
+ /* WaPipelineFlushCoherentLines:tgl */
+ wa_write_or(wal,
+ GEN12_L3SQCREG2,
+ GEN12_LQSC_FLUSH_COHERENT_LINES);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70872c9391ff..0a2657ce284f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7747,6 +7747,9 @@ enum {
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
+#define GEN12_L3SQCREG2 _MMIO(0xb104)
+#define GEN12_LQSC_FLUSH_COHERENT_LINES (1 << 24)
+
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22472f2bd31b..b966c736da69 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
+ if (IS_GEN(dev_priv, 12))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2b839acfa0f6..940445d052a4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct
intel_uncore_forcewake_domain *d,
* the fallback ack.
*
* This workaround is described in HSDES #1604254524 and it's known as:
- * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
* although the name is a bit misleading.
*/
--
2.21.0
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