>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 30, 2019 1:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nik...@intel.com>; ville.syrj...@linux.intel.com;
>Shankar, Uma
><uma.shan...@intel.com>; Kulkarni, Vandita <vandita.kulka...@intel.com>
>Subject: [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for
>video
>mode
>
>Blanking packet bit will control whether the transcoder allows the link to
>enter the LP
>state during BLLP regions (assuming there is enough time), or whether it will
>keep the
>link in the HS state with a Blanking Packet
Looks good to me.
Reviewed-by: Uma Shankar <uma.shan...@intel.com>
>Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 6 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>b/drivers/gpu/drm/i915/display/icl_dsi.c
>index eaf2779b89b8..ae33639d48ba 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -685,6 +685,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder
>*encoder,
> break;
> }
>
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ if (is_vid_mode(intel_dsi))
>+ tmp |= BLANKING_PACKET_ENABLE;
>+ }
>+
> /* program DSI operation mode */
> if (is_vid_mode(intel_dsi)) {
> tmp &= ~OP_MODE_MASK;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index
>d2b76121d863..1a847f443ef7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10979,6 +10979,7 @@ enum skl_power_gate {
> #define CALIBRATION_DISABLED (0x0 << 4)
> #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
> #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
>+#define BLANKING_PACKET_ENABLE (1 << 2)
> #define S3D_ORIENTATION_LANDSCAPE (1 << 1)
> #define EOTP_DISABLED (1 << 0)
>
>--
>2.21.0.5.gaeb582a
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