On Thu, 2013-06-13 at 22:46 +0200, Daniel Vetter wrote:
> On Thu, Jun 13, 2013 at 10:26 PM, Imre Deak <imre.d...@intel.com> wrote:
> >> + if (HAS_PCH_SPLIT(dev)) {
> >> + assert_fdi_rx_pll_disabled(dev_priv, pipe);
> >> + assert_shared_dpll_disabled(dev_priv,
> >> + intel_crtc_to_shared_dpll(crtc));
> >
> > I think if we pick a shared PLL that is currently used by another port
> > this will trigger. Should the PLL selection be limited to non-shared
> > PLLs for LVDS?
>
> LVDS has a special clock selection setting and there's only eve one
> LVDS port on any given machine. Which means we won't ever be able to
> share the dpll with anything else.
Ok, I should've looked closer and realize that dpll matching is not only
about rate matching, but also matching the rest of dpll mode bits. But
it's clear now we can't get here with a shared dpll, so the assert is
ok.
> I'll add this to the commit message when I resend the patch to fix up
> the debug output.
Ok.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
