Quoting Mika Kuoppala (2020-05-06 16:58:55) > Aux table invalidation can fail on update. So > next access may cause memory access to be into stale entry. > > Proposed workaround is to invalidate entries between > all batchbuffers. > > v2: correct register address (Yang) > > References bspec#43904, hsdes#1809175790 > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Chuansheng Liu <chuansheng....@intel.com> > Cc: Rafael Antognolli <rafael.antogno...@intel.com> > Cc: Yang A Shi <yang.a....@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
I only hear good things about v3, so Acked-by: Chris Wilson <ch...@chris-wilson.co.uk> > @@ -2526,6 +2526,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define HSW_GTT_CACHE_EN _MMIO(0x4024) > #define GTT_CACHE_EN_ALL 0xF0007FFF > #define GEN7_WR_WATERMARK _MMIO(0x4028) > +#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) > +#define AUX_INV REG_BIT(0) > #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) > #define ARB_MODE _MMIO(0x4030) > #define ARB_MODE_SWIZZLE_SNB (1 << 4) 4024, 4028, 4208, 402C, 4030. Something seems not quite right. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
