On Thu, 2021-02-18 at 00:14 +0200, Ville Syrjälä wrote:
> On Wed, Feb 17, 2021 at 05:24:03PM +0000, Souza, Jose wrote:
> > On Fri, 2021-02-12 at 23:13 +0200, Ville Syrjälä wrote:
> > > On Fri, Feb 12, 2021 at 07:44:22PM +0000, Souza, Jose wrote:
> > > > On Fri, 2021-02-12 at 20:35 +0200, Ville Syrjälä wrote:
> > > > > On Fri, Feb 12, 2021 at 10:22:01AM -0800, José Roberto de Souza wrote:
> > > > > > Found a system were firmware/BIOS left the plane_res_b and
> > > > > > plane_res_l
> > > > > > set with non-zero values for disable planes.
> > > > >
> > > > > It pretty much happens always since the reset value is not zero.
> > > > > IIRC we made the state chcker pedantic enough to complain about
> > > > > that, so we need to clean it up.
> > > >
> > > > Are you planning to fix it soon?
> > >
> > > Fix what exactly? I guess you're seeing an actual problem of some sort?
> >
> > Your comment above made me understand that you were planning to fix this
> > plane watermark mismatches for disabled planes in other way other than what
> > this patch does.
> > Or should we proceed with this solution?
>
> There should be no mismatches with the current scheme.
> We explicitly program wms to 0 for disabled planes.
>
It still happens when we take over the state that BIOS/firmware left.
[ 118.222939] [drm:drm_atomic_commit] committing 00000000676e6290
[ 118.241712] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight
[i915]] set backlight PWM = 96000
[ 118.242314] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling
FBC on pipe A
[ 118.242726] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] reserved
16588800 bytes of contiguous stolen space for FBC, threshold: 1
[ 118.243020] i915 0000:00:02.0: [drm:intel_fbc_enable [i915]] Enabling FBC on
pipe A
[ 118.257685] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257698] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257706] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257714] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257721] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257729] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257737] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 2
level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257745] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A
plane 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257753] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe
A plane 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257761] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257769] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257776] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257784] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257792] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257800] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257807] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 3
level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257815] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A
plane 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257823] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe
A plane 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257920] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257929] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257939] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257949] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257956] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257965] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257975] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 4
level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257984] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A
plane 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.257993] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe
A plane 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258002] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 0 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258011] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 1 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258020] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 2 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258029] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 3 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258037] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 4 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258046] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258054] i915 0000:00:02.0: [drm] *ERROR* mismatch in WM pipe A plane 5
level 6 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258063] i915 0000:00:02.0: [drm] *ERROR* mismatch in trans WM pipe A
plane 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258073] i915 0000:00:02.0: [drm] *ERROR* mismatch in SAGV trans WM pipe
A plane 5 (expected e=0 b=0 l=0, got e=0 b=7 l=1)
[ 118.258494] i915 0000:00:02.0: [drm:verify_connector_state [i915]]
[CONNECTOR:381:eDP-1]
[ 118.259022] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]]
[CRTC:116:pipe A]
[ 118.259811] i915 0000:00:02.0: [drm:intel_ddi_read_func_ctl [i915]]
[ENCODER:380:DDI B/PHY B] Fec status: 0
[ 118.260284] i915 0000:00:02.0: [drm:verify_single_dpll_state [i915]] DPLL 0
Other option would be to call intel_plane_disable_noatomic() even for
non-visible planes:
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6014c643a89d..20b3844c8875 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15882,11 +15882,7 @@ static void intel_sanitize_crtc(struct intel_crtc
*crtc,
/* Disable everything but the primary plane */
for_each_intel_plane_on_crtc(dev, crtc, plane) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(plane->base.state);
-
- if (plane_state->uapi.visible &&
- plane->base.type != DRM_PLANE_TYPE_PRIMARY)
+ if (plane->base.type != DRM_PLANE_TYPE_PRIMARY)
intel_plane_disable_noatomic(crtc, plane);
}
What do you think?
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