Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.

Signed-off-by: Michael Cheng <michael.ch...@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c                 | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c                  |  2 +-
 drivers/gpu/drm/i915/gt/intel_ppgtt.c                |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c    |  2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
                                pd = pdp->entry[gen8_pd_index(idx, 2)];
                        }
 
-                       clflush_cache_range(vaddr, PAGE_SIZE);
+                       drm_clflush_virt_range(vaddr, PAGE_SIZE);
                        vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 
1)));
                }
        } while (1);
-       clflush_cache_range(vaddr, PAGE_SIZE);
+       drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
        return idx;
 }
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
                        }
                } while (rem >= page_size && index < I915_PDES);
 
-               clflush_cache_range(vaddr, PAGE_SIZE);
+               drm_clflush_virt_range(vaddr, PAGE_SIZE);
 
                /*
                 * Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
                                              I915_GTT_PAGE_SIZE_2M)))) {
                        vaddr = px_vaddr(pd);
                        vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
-                       clflush_cache_range(vaddr, PAGE_SIZE);
+                       drm_clflush_virt_range(vaddr, PAGE_SIZE);
                        page_size = I915_GTT_PAGE_SIZE_64K;
 
                        /*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct 
i915_address_space *vm,
                                for (i = 1; i < index; i += 16)
                                        memset64(vaddr + i, encode, 15);
 
-                               clflush_cache_range(vaddr, PAGE_SIZE);
+                               drm_clflush_virt_range(vaddr, PAGE_SIZE);
                        }
                }
 
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct 
i915_address_space *vm,
 
        vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
        vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
-       clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+       drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
 static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index cc561cfae808..bbe33794b34d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs 
*engine)
        sanitize_hwsp(engine);
 
        /* And scrub the dirty cachelines for the HWSP */
-       clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+       drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
        intel_engine_reset_pinned_contexts(engine);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, 
unsigned int count)
        void *vaddr = __px_vaddr(p);
 
        memset64(vaddr, val, count);
-       clflush_cache_range(vaddr, PAGE_SIZE);
+       drm_clflush_virt_range(vaddr, PAGE_SIZE);
 }
 
 static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
        u64 * const vaddr = __px_vaddr(pdma);
 
        vaddr[idx] = encoded_entry;
-       clflush_cache_range(&vaddr[idx], sizeof(u64));
+       drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
 }
 
 void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
        sanitize_hwsp(engine);
 
        /* And scrub the dirty cachelines for the HWSP */
-       clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+       drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
 
        intel_engine_reset_pinned_contexts(engine);
 }
-- 
2.25.1

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