[Intel-gfx] [PATCH CI v3 2/3] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

[José Roberto de Souza]

From: Caz Yokoyama <caz.yokoy...@intel.com>

Alderlake-P has different MBUS DBOX BW and B credits than other
platforms, so here setting it properly.

BSpec: 49213
BSpec: 50343
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoy...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8501929bca3aa..e5f12f2040af8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1845,7 +1845,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc 
*crtc, bool joined_mbus)
        else
                val |= MBUS_DBOX_A_CREDIT(2);
 
-       if (DISPLAY_VER(dev_priv) >= 12) {
+       if (IS_ALDERLAKE_P(dev_priv)) {
+               val |= MBUS_DBOX_BW_CREDIT(2);
+               val |= MBUS_DBOX_B_CREDIT(8);
+       } else if (DISPLAY_VER(dev_priv) >= 12) {
                val |= MBUS_DBOX_BW_CREDIT(2);
                val |= MBUS_DBOX_B_CREDIT(12);
        } else {
-- 
2.35.1