[Intel-gfx] [PATCH 2/3] drm/i915: Move DG2 tuning to the right function

[Lucas De Marchi]

Use gt_tuning_settings() for the recommended tunings rather than the one
for workarounds.

Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index eb6cc4867d67..389bfcd299af 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1653,13 +1653,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
        /* Wa_14014830051:dg2 */
        wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
-       /*
-        * The following are not actually "workarounds" but rather
-        * recommended tuning settings documented in the bspec's
-        * performance guide section.
-        */
-       wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
-
        /* Wa_14015795083 */
        wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 
@@ -1752,8 +1745,10 @@ static void gt_tuning_settings(struct intel_gt *gt, 
struct i915_wa_list *wal)
                wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
        }
 
-       if (IS_DG2(gt->i915))
+       if (IS_DG2(gt->i915)) {
                wa_mcr_write_or(wal, XEHP_L3SCQREG7, 
BLEND_FILL_CACHING_OPT_DIS);
+               wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+       }
 }
 
 static void
-- 
2.39.0